Many microdevices, such as integrated circuits, have become so complex that these devices cannot be manually designed. For example, even a simple microprocessor may have millions and millions of transistors that cooperate to form the components of the microprocessor. As a result, electronic design automation tools have been created to assist circuit designers in designing a circuit, and then analyzing the circuit design before it is manufactured.
Designing and fabricating microcircuit devices involve many steps during a ‘design flow’ process. These steps are highly dependent on the type of microcircuit, its complexity, the design team, and the fabricator or foundry that will manufacture the microcircuit from the design. Several steps are common to most design flows, however. First, a design specification is modeled logically, typically in a hardware design language (HDL). Once a logical design has been created, various logical analysis processes are performed on the design to verify its correctness. More particularly, software and hardware “tools” verify that the logical design will provide the desired functionality at various stages of the design flow by running software simulators and/or hardware emulators, and errors are corrected. For example, a designer may employ one or more functional logic verification processes to verify that, given a specified input, the devices in a logical design will perform in the desired manner and provide the appropriate output.
After the logical design is deemed satisfactory, it is converted into physical design data by synthesis software. This physical design data or “layout” design data will include geometric elements representing the image that will be written onto a mask used to fabricate the desired microcircuit device in a photolithographic process at a foundry. While these geometric elements may be of any shape, with conventional mask or reticle writing tools the geometric elements typically will be polygons or line edges used to form polygons. Thus, the layout design data usually includes polygon data describing the features of polygons in the design. It is very important that the physical design information accurately embody the design specification and logical design for proper operation of the device. Accordingly, after it has been created during a synthesis process, the physical design data is compared with the original logical design schematic in a process sometimes referred to as a “layout-versus-schematic” (LVS) verification process.
Once the correctness of the logical design has been verified, and geometric data corresponding to the logical design has been created in a layout design, the geometric data then may be analyzed. For example, because the physical design data is employed to create masks used at a foundry, the data must conform to the foundry's requirements. Each foundry specifies its own physical design parameters for compliance with their processes, equipment, and techniques. Accordingly, the design flow may include a process to verify that the design data complies with the specified parameters. During this process, the physical layout of the circuit design is compared with design rules in a process commonly referred to as a “design rule check” (DRC) process. In addition to rules specified by the foundry, the design rule check process may also check the physical layout of the circuit design against other design rules, such as those obtained from test chips, general knowledge in the industry, previous manufacturing experience, etc. Examples of electronic design automation “verification” tools that perform these types of electronic design automation verification processes include the Calibre family of software tools available from Mentor Graphics Corporation of Wilsonville, Oreg.
After a designer has used one or more geometry analysis processes to verify that the physical layout of the circuit design is satisfactory, the designer may then perform one or more simulation processes to simulate the operation of a manufacturing process, in order to determine how the design will actually be realized by that particular manufacturing process. A simulation analysis process may additionally modify the design to address any problems identified by the simulation. For example, some design flows may employ one or more processes to simulate the image formed by the physical layout of the circuit design during a photolithographic process, and then modify the layout design to improve the resolution of the image that it will produce during a photolithography process.
These resolution enhancement techniques (RET) may include, for example, modifying the physical layout using optical proximity correction (OPC) or by the addition of sub-resolution assist features (SRAF). Other simulation analysis processes may include, for example, phase shift mask (PSM) simulation analysis processes, etch simulation analysis processes and planarization simulation analysis processes. Etch simulation analysis processes simulate the removal of materials during a chemical etching process, while planarization simulation processes simulate the polishing of the circuit's surface during a chemical-mechanical etching process. These simulation analysis processes may identify, for example, regions where an etch or polishing process will not leave a sufficiently planar surface. These simulation analysis processes may then modify the physical layout design to, e.g., include more geometric elements in those regions to increase their density.
Once a physical layout design has been finalized, the geometric elements in the design are formatted for use by a mask or reticle writing tool. Masks and reticles typically are made using tools that expose a blank reticle or mask substrate to an electron or laser beam (or to an array of electron beams or laser beams), but most mask writing tools are able to only “write” certain kinds of polygons, however, such as right triangles, or rectangles or other trapezoids. Moreover, the sizes of the polygons are limited physically by the maximum beam (or beam array) size available to the tool. Accordingly, the larger polygons in a physical layout design data will typically be “fractured” into the smaller, more basic polygons that can be written by the mask or reticle writing tool.
One process that is desirable for analyzing integrated circuit designs is the ability to verify the presence of appropriate electrostatic damage protection circuitry. Electrostatic damage protection circuitry protects functional circuit from sudden spikes of electrostatic power. In addition to confirming that the integrated circuit includes the desired circuit components (e.g., one or more electrostatic damage protection diodes), it is also useful to confirm that the interconnection lines connecting those circuit components do not exceed one or more maximum impedance components. For example, it would be useful to confirm that the total resistance from an input/output pad, through an electrostatic damage protection circuit, to the location on the ground plane layer where the functional circuit is grounded does not exceed the total resistance from the from an input/output pad through the functional circuit to the ground plane layer. If it does, then an electrostatic discharge will circumvent the electrostatic damage protection circuit, and potentially damage the functional circuit.
Ideally, the resistance of the interconnect lines connecting the electrostatic damage protection circuit components can be determined from the thickness and distance of the interconnect lines. As a practical matter, however, the interconnect lines may have long paths and vary in width along their lengths, making their resistance difficult to determine. Further, the interconnect lines could be connected to other components along their length, such as transistor contacts, which also may impact the value of their impedance components.
While some electronic design automation tools can perform a parasitic extraction analysis on interconnect lines, in order to determine one or more impedance component values of the lines, the calculations required to perform this extraction process are extremely resource intensive and time consuming. Typically, the parasitic extraction analysis process would transform each interconnect being analyzed in the design into a resistor, such that each contact with an interconnect line and each turn of an interconnect line is treated as a separate resistor, capacitor and/or inductor, depending upon the impedance component being calculated. Each ground plane of the design, which is conventionally formed by a grid of interconnect lines, would then become a huge network of resistors, capacitors and/or inductors. In order to determine if the interconnect lines associated with an electrostatic damage protection circuit had less than a maximum specified impedance component value, the analysis process would then walk through the resistor, capacitor and/or inductance network representing the entire circuit design to identify all possible connections to the electrostatic damage protection circuit and their associated parasitic values